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7 cool things to know about Intel process & packaging innovation

Peter Krass's picture

by Peter Krass on 08/25/2020
Blog Category: devices

During Intel’s virtual Architecture Day 2020, held earlier this month, Intel architects took attendees on a deep dive into the company’s innovations in component processes and packaging.

These innovations will be needed to keep up with the explosion in data volume. The industry is now pushing against the limits of Moore’s Law. Market watcher IDC predicts the world’s data volume will hit 175 ZB by 2025 — about 3x what it is today.

“There’s a problem with lots of data,” Raja Koduri, Intel’s chief architect, told the Architecture Day audience. “Data that is not analyzed is not useful. But analysis on a ton of data requires a ton of compute.”

Raja Koduri, Intel's chief architect

Intel’s Raja Koduri: “Analysis on a ton of data requires a ton of compute”

But just as more compute power is needed, advances in transistor performance/dollar and performance/watt are slowing. The result? “Extracting exponential value from transistor technology,” Koduri said, “now requires new approaches across the whole stack.”

7 new approaches

To that end, here are 7 process and packaging innovations that Intel believes will deliver that new approach. All were profiled during Intel’s Architecture Day 2020:

Foveros: Intel’s approach to 3D stacking. With Foveros, processors are built in a new way: not flat in two dimensions, but stacked in three. The first Intel processor to use this approach was Lakefield, introduced this past June.

FinFET: Intel was the first to introduce 3D transistor technology, and it has now introduced the 3rd generation of this technology at the 10nm mode. This hyperscaling allows a roughly 2.7x improvement in density over the prior mode. This was done not only by reducing the transistor size, but also with metal interconnects, cell-level and more.

SuperFin: This 10nm technology combines Intel’s enhanced FinFET transistors with Super metal insulator metal capacitor. SuperFin technology offers enhanced epitaxial source/drain, improved gate process and additional gate pitch to enable greater performance. It’s being used in Intel’s forthcoming Tiger Lake mobile processors.

COAG: Short for Contact Over Active Gate, this process allows for smaller cells and improved transistors. Contacts are placed directly over the active fins, which allows Intel to shrink the cell-area scaling.

EMIB: Intel's Embedded Multi-die Interconnect Bridge technology has been in the works for years. It's essentially a small bridge die with multiple routing layers, embedded in a standard organic package. One early implementation was Intel’s Kaby Lake G processor, which uses EMIB for a mix-and-match approach on a SoC.

AIB: Advanced Interface Bus is Intel’s die-to-die interconnect standard for high-bandwidth, low-power connections between chiplets. AIB 2.0, expected in early 2021, should deliver gains that include expanding bandwidth/wire from 2 Gbps to 6.4 Gbps. Also, Intel has released an open-source AIB generator that’s now available to help other companies use this standard

Co-EMIB: A future Intel technology, this will combine Foveros with EMIB for increased partitioning opportunities. Speaking at Intel Architecture Day, Ramune Nagisetty, Intel’s director of product and process integration, said this approach should be especially attractive for both data-center and high performance computing (HPC) applications.

Learn more:

> Watch the Intel Architecture Day 2020 replay video (process and packaging discussion begins at 14:03)

> Watch the Intel SuperFin explainer video

> Download the Intel Architecture Day 2020 presentation slides (PDF)

 

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