Back to top

The indispensable source for professionals who create, implement and service technology solutions for entrepreneurs to enterprise.

In the Zone

Develop custom FPGA platforms & workloads with Intel OFS

Peter Krass's picture

by Peter Krass on 11/15/2022
Blog Category: cloud-and-data-centers

If you or your customers want to get into FPGA development, but have hesitated due to the technology’s complexity, Intel is here to help. 
 
Intel’s latest solution is the Open FPGA Stack (Intel OFS). It’s a hardware and software infrastructure designed to give you and your customers an efficient and easy way to develop custom FPGA platforms and workloads using third-party, custom and Intel boards.
 
Intel OFS is a scalable framework delivered through Git repositories. (Git is an open source repository.) Intel OFS can help you and your customers develop FPGA applications quickly with modular, composable source code that can be either used as-is or customized. 
 
This is about a lot more than just Intel. The upstreamed Linux kernel drivers and user space of Intel OFS are being adopted by a growing list of software distribution vendors to provide native support in their OS distributions. Also, a growing ecosystem of partners now offer Intel OFS-enabled boards and workloads. End users can begin to evaluate and create proof-of-concepts (PoCs) using these OFS-based solutions.
 
Components checklist
 
Intel OFS has been designed to address challenges of all 3 personas typically involved in FPGA development: board developers; software developers; and application developers. To do this, Intel OFS comprises 2 sets of deliverables: hardware and software. 
 
The hardware includes an Acceleration Functional Unit (AFU) region; example FPGA interface manager (FIM); board management controller (BMC); and high-level design (HLD) shim for oneAPI enablement.
 
Software deliverables of Intel OFS include open source, upstreamed Linux kernel drivers; and Open Programmable Application Engine (OPAE) libraries, tools and APIs. There’s also a universal verification methodology (UVM) test environment to jump-start verification; it’s also provided through Git repositories. 
 
Detailed technical documentation—including getting started guides and user guides for various OFS subsystems—are co-located with the source-code and verification environment on GitHub. 
 
User profile: SAP
 
One company already working with Intel OFS is SAP. Developers at the company have created a PoC for a cloud-based solution known as Compression as a Service (CaaS).
 
CaaS is intended for use with SAP’s HANA relational database management system. Columnar data in SAP HANA is encoded with dictionaries that can contain huge amounts of data—so much data, in fact, that to minimize memory requirements, it needs to be compressed.
 
Typically, this compression is done with algorithms that arrange the data in a single block. Then, to access any of the data, the entire block must be decompressed. This uses a lot of compute power and takes a lot of time. 
 
One alternative is a compression algorithm known as Re-Pair (short for recursive pairing). However, Re-Pair is compute-intensive. When implemented on a centralized CPU, it’s also slow. 
 
The solution? Run Re-Pair instead on an FPGA. An FPGA’s programmable fabric can be configured to perform algorithmic processing in a massively parallel fashion. The result: Algorithms such as Re-Pair can be executed quickly while consuming relatively little power. 
 
As part of this work, SAP used the provided Intel OFS infrastructure and documentation to quickly port their Re-Pair compression workload to the Intel FPGA PAC D5005 hardware platform. 
 
To complete the PoC sooner, SAP leveraged key features of Intel OFS. These included upstreamed FPGA kernel drivers, a modular and customizable FIM, a Partial Reconfiguration (PR) design flow, and an HLD shim to support oneAPI kernels. 
 
Reference platforms 
 
Intel OFS has been developed and validated using the Intel FPGA PAC D5005 and Intel N6000 ADP as hardware reference platforms for the Intel OFS Intel Stratix 10 and Intel Agilex FPGA code lines:
 
> Intel FPGA Programmable Acceleration Card (PAC) D5005: Intel Stratix 10 SX FPGA, 32GB of DDR4 memory, 10/25/40/100GbE Ethernet, and PCIe Gen3 x16 connectivity.
 
> Intel FPGA SmartNIC N6000-PL Platform: Intel Agilex FPGA, 17GB of DDR4 memory, up to 2x100GbE Ethernet, and PCIe Gen4 x16 connectivity.
 
Users can leverage these reference platforms with the Intel OFS hardware and software code for initial code bring-up before modifying and porting to an Intel-FPGA based third-party, Intel-branded or custom platform. 
 
While these reference platforms are recommended starting points, their use is not required. Instead, hardware developers can choose to clone the repositories and immediately begin porting to their own hardware. 
 
Intel has big plans for its FPGA customers with Intel OFS. And with the ecosystem gearing up to release more OFS-enabled boards and workloads, the work is just getting started. 
 
Now’s the time to get comfortable with FPGA technology. Intel is offering training and other resources to help you do just that:
 
> Browse Intel FPGA acceleration cards and OFS resources
 
> Meet Intel FPGAs and other programmable devices
 
> Read more: SAP prototypes containerized compression workload leveraging the Intel OFS infrastructure
 
> Find FPGA partners and offerings in Intel Solutions Marketplace
 
> Get trained and certified with Intel Partner University’s FPGA Fundamentals Competency
 
Back to top